Timeline for ASIC designs for high-efficiency Bitcoin miners
Current License: CC BY-SA 3.0
6 events
| when toggle format | what | by | license | comment | |
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| Mar 27, 2016 at 4:45 | history | edited | Jeanne Holm | CC BY-SA 3.0 |
To clarify question
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| Mar 26, 2016 at 17:05 | comment | added | kenorb | I'm looking for open data in form of some logic representation (such as HDL) which can be used to simulate such miners for ASIC chip. Similar to Software to simulate ASIC chip logic, but I'm looking for available data. | |
| Mar 26, 2016 at 17:03 | history | edited | kenorb | CC BY-SA 3.0 |
added 216 characters in body
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| Mar 26, 2016 at 16:27 | review | Close votes | |||
| Mar 27, 2016 at 4:45 | |||||
| Mar 26, 2016 at 16:08 | comment | added | philshem | Is this information or data? | |
| Mar 26, 2016 at 4:32 | history | asked | kenorb | CC BY-SA 3.0 |